1. Field
Embodiments of the present invention relate to transistors, and in particular to improving the speed of transistors.
2. Discussion of Related Art
A typical metal-oxide-semiconductor field effect transistor (MOSFET) has a gate, a drain, and a source formed in or on a semiconductor wafer. When a voltage Vg is applied to the gate that is greater than the threshold voltage Vt of the transistor, the transistor turns on and current flows in a conducting layer formed below the gate and between the source and drain. When the voltage Vg applied to the gate that is less than the threshold voltage Vt of the transistor, the transistor turns off and current stops flowing in the channel. The current that flows in the channel is the drive current ID, sometimes called saturation drive current or linear drive current. In the MOSFET equation, saturation drive current (ID) is expressed by
ID=W/L xcexc Cox(Vgxe2x88x92Vt)2 
where W is the width of the gate, L is the length of the gate, Cox is the gate capacitance, Vg is the gate voltage, Vt is the threshold voltage for the transistor, xcexc is electron mobility in the channel, in percent change. As the equation indicates, as the electron mobility increases, drive current increases.
MOSFETS can be either n-type metal oxide semiconductor (NMOS) transistors or p-type metal oxide semiconductor (PMOS) transistors and usually a combination of NMOS transistors and PMOS transistors are present in a single integrated circuit device. Integrated circuit technology is advancing at a rapid pace and transistor technology must keep up.
One method for improving NMOS transistor performance is to add a layer of high stress dielectric material to the transistor. Adding a layer of high stress dielectric material to the transistor introduces stress in the device. Introducing stress by adding a layer of high stress dielectric material to the transistor increases electron mobility in the transistor. Increasing electron mobility causes transistor drive current to improve. This technique, i.e., adding a layer of high stress dielectric material, increases transistor fabrication process complexity, however, and can degrade PMOS transistor performance.